Recently, as semiconductor devices have become highly integrated, the channel distance between the source and the drain of a semiconductor device has becomes increasingly shortened. As the channel distance has shortened, the electric potential across the channel from the source region to the drain region has increased such that a strong horizontal electric field is generated between the source and drain regions, whereby the threshold voltage of the channel area is destabilized. This electric field causes a punchthrough phenomenon which degrades the characteristics of the semiconductor device. This punchthrough phenomenon is called the “short channel effect.”
Various techniques have been proposed to solve these problems. These proposed techniques include: reducing the thickness of the pad oxide layer, increasing the impurity concentration of the channel region, forming the source/drain regions shallow, or forming the device on a silicon-on-insulator (SOI) substrate. Among these approaches, the techniques of reducing the thickness of the pad oxide layer and/or increasing the impurity concentration of the channel region have shortcomings in that they are sensitive to process variations and are difficult to control accurately.
In order to solve these issues, an elevated contact technique for forming the source/drain regions on an epitaxial layer has been proposed. (The epitaxial layer is formed on the surface of the substrate through a self-align technique.) FIG. 1A to FIG. 1D are cross-sectional views illustrating a conventional process for fabricating a semiconductor device having an elevated contact structure.
Referring to FIG. 1A, a device isolation region 12 is formed in a predetermined area of a semiconductor substrate 10. A pad oxide layer 14 and a gate 16 are sequentially formed on the semiconductor substrate 10.
Referring to FIG. 1B, low concentration doping regions 18 are formed in predetermined areas of the substrate 10 by doping conductive impurity ions into the desired areas. Spacers 20 are formed on the sidewalls of the gate 16.
Referring to FIG. 1C, an epitaxial layer 22 is selectively developed on the semiconductor substrate 10. In the illustrated example, the epitaxial layer 22 is developed to a predetermined height on opposite sides of the gate 16. The epitaxial layer 22 is only formed on the surface of the silicon layer. It is not formed on the dielectric layers of the spacers 20 and/or the device isolation regions 12.
Referring to FIG. 1D, the source and drain regions 24 are formed by doping and diffusing the conductive impurity ions in predetermined regions of the substrate 10 and the epitaxial regions 22.
In a semiconductor device having an elevated contact formed via the above described technique, the epitaxial layer 22 is selectively developed in predetermined areas of the semiconductor substrate 10. In particular, the epitaxial layer 22 is developed at contact area(s) between the spacers 20 and the device isolation areas 12 at relatively slow speed such that the thickness is less in these slow developing areas than in other regions. Each of these areas of reduced thickness is called a facet (F).
However, if the impurity ions for forming the source and the drain are injected into the epitaxial layer 22 having the facet structure, the injection depth is shallow. As a result, the impurities can diffuse to the low concentration doping region(s) at the facet area(s) F which have relatively shallow thickness. This diffusion can degrade the reliability of the resulting semiconductor device.
To clarify multiple layers and regions, the thickness of the layers are enlarged in the drawings. Wherever possible, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. As used in this patent, stating that any part (e.g., a layer, film, area, or plate) is in any way positioned on (e.g., positioned on, located on, disposed on, or formed on, etc.) another part, means that the referenced part is either in contact with the other part, or that the referenced part is above the other part with one or more intermediate part(s) located therebetween. Stating that any part is in contact with another part means that there is no intermediate part between the two parts.